The present invention relates to a substrate bias voltage generator circuit, and more particularly, to a substrate bias voltage generator circuit having a circuit for detecting a substrate bias voltage.
A bias voltage is applied to the substrate of a semiconductor memory device in order to prevent a parasitic p-n junction from being forward biased by undershooting of an externally inputted signal, or to increase the speed of operation by enlarging a depletion layer a p-n junction to reduce parasitic capacitance.
Inexpensive, large capacity semiconductor memory devices have been desired so as to meet the rapid profusion of machines such as personal computers. An example of such inexpensive, large capacity semiconductor memory devices is a dynamic random access memory (DRAM). DRAMs are required to be backed up to maintain their data. For a battery back-up, it is necessary to reduce the current consumption during a standby state. Several circuits in a DRAM will consume current during the standby state. Of these circuits, a substrate bias voltage generator circuit consumes most of the current. It is therefore important to reduce current consumption of the substrate bias voltage generator circuit.